The present invention relates to a frame-synchronizing-signal capturing circuit of a receiver, particularly to a frame-synchronizing-signal capturing circuit of a receiver for capturing a frame-synchronizing-signal portion in two series of I and Q symbol-stream data obtained by receiving and demodulating a signal to be PSK-modulated in which a BPSK-modulated frame-synchronizing signal or a BPSK-modulated frame-synchronizing signal and a superframe-identifying signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and a BPSK-modulated digital signal are time-multiplexed in accordance with a hierarchical transmission system or the like.
Practical use of digital satellite TV broadcast is advanced which conforms to a plurality of modulation systems having required C/Ns different from each other such as hierarchical transmission systems in which a wave to be 8PSK-modulated, a wave to be QPSK-modulated, and a wave to be BPSK-modulated are time-multiplexed and repeatedly transmitted every frame.
FIG. 7 is an illustration showing a frame configuration of a hierarchical transmission system. One frame is constituted of a frame-synchronizing-signal interval comprising 32 BPSK-modulated symbols, a TMCC (Transmission and Multiplexing Configuration Control) signal interval comprising 128 BPSK-modulated symbols to identify a transmission multiple configuration, a superframe-identifying signal interval comprising 32 symbols, a main signal interval of 203 8PSK(trellis-coding-8PSK)-modulated symbols, a burst symbol signal (BS) interval of four symbols in which a pseudo random noise (PN) signal is BPSK-modulated, a main signal interval of 203 8PSK(trellis-codec-8PSK)-modulated symbols, a burst symbol signal (BS) interval of four symbols in which a pseudo random noise (PN) signal is BPSK-modulated, a main signal interval of 203 QPSK-modulated symbols, a burst symbol signal (BS) interval of four symbols in which a pseudo random noise (PN) signal is BPSK-modulated, a main signal interval of 203 QPSK-modulated symbols, and a burst symbol signal (BS) interval of four BPSK-modulated symbols in order.
FIG. 8 is an illustration showing a superframe configuration according to the hierarchical transmission system. One superframe is constituted of 8 consecutive frames and a superframe-identifying signal serves as information for identifying a superframe. The 192 symbols from the head of a frame-synchronizing-signal interval up to the end of a superframe-identifying-signal interval are also referred to as a header.
The first-half 20 symbols of a frame-synchronizing-signal interval of 32 symbols are actually used as a frame-synchronizing signal. This is because the first-half 20 symbols in a 32-symbol interval to be originally used for another purpose serve as a unique word and the unique word is used as a frame-synchronizing signal. A frame-synchronizing signal comprising the 20 symbols is also referred to as xe2x80x9cW1xe2x80x9d which is shown by the following expression.                     W1        =                  (                      S0S1            ⁢                          xe2x80x83                        ⁢            …            ⁢                          xe2x80x83                        ⁢            S18S19                    )                                        =                  (          11101100110100101000          ⁢                      xe2x80x83                    )                    
(This is transmitted from the S0 side.)
Similarly, the first-half 20 symbols of a superframe-identifying signal of 32 symbols are actually used as a superframe-identifying signal. This is also because the first-half 20 symbols of a 32-symbol interval to be originally used for another purpose serve as a unique word and the unique word is used as a superframe-identifying signal. The first frame of a superframe in the superframe-identifying signal comprising 20 symbols is also referred to as xe2x80x9cW2xe2x80x9d which is shown by the following expression.                     W2        =                  (                      U0U1            ⁢                          xe2x80x83                        ⁢            …            ⁢                          xe2x80x83                        ⁢            U18U19                    )                                        =                  (          00001011011001110111          ⁢                      xe2x80x83                    )                    
(This is transmitted from the U0 side.)
Frames other than the first frame of a superframe in a superframe-identifying signal are also referred to as xe2x80x9cW3xe2x80x9d which is obtained by inverting each bit of W2 and W3 is shown by the following expression.                     W3        =                  (                      V0V1            ⁢                          xe2x80x83                        ⁢            …            ⁢                          xe2x80x83                        ⁢            V18V19                    )                                        =                  (          11110100100110001000          ⁢                      xe2x80x83                    )                    
(This is transmitted from the V0 side.)
Then, mapping for each modulation system at the transmission side is described below by referring to FIGS. 9A to 9C. FIG. 9A shows signal point arrangements on I-Q phase plane (also referred to as I-Q vector plane or I-Q signal space diagram) when using 8PSK for a modulation system. The 8PSK modulation system transmits a three-bit digital signal (abc) by one symbol and combinations of bits constituting one symbol include such eight ways as (000), (001), (010), (011), (100), (101), (110), and (111). These three-bit digital signals are converted into signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d on the transmission-side I-Q phase plane in FIG. 9A and this conversion is referred to as 8PSK mapping.
In case of the example shown in FIG. 9A, a bit string (000) is converted into a signal point arrangement xe2x80x9c0xe2x80x9d, a bit string (001) into a signal point arrangement xe2x80x9c1xe2x80x9d, a bit string (011) into a signal point arrangement xe2x80x9c2,xe2x80x9d a bit string (010) into a signal point arrangement xe2x80x9c3xe2x80x9d, a bit string (100) into a signal point arrangement xe2x80x9c4xe2x80x9d, a bit string (101) into a signal point arrangement xe2x80x9c5xe2x80x9d, a bit string (111) into a signal point arrangement xe2x80x9c6xe2x80x9d, and a bit string (1 10) into a signal point arrangement xe2x80x9c7xe2x80x9d.
FIG. 9B shows signal point arrangements at I-Q phase plane when using QPSK for a modulation system. The QPSK modulation system transmits a two-bit digital signal (de) by one symbol and combinations of bits constituting the symbol include such four ways as (00), (01), (10), and (11). In case of the example in FIG. 9B, a bit string (00) is converted into a signal point arrangement xe2x80x9c1,xe2x80x9d a bit string (01) into a signal point arrangement xe2x80x9c3xe2x80x9d, a bit string (11) into a signal point arrangement xe2x80x9c5xe2x80x9d, and a bit string (10) into a signal point arrangement xe2x80x9c7xe2x80x9d.
FIG. 9C shows signal point arrangements at the time of using BPSK for a modulation system. The BPSK modulation system transmits a one-bit digital signal (f) by one symbol. In case of the digital signal (f), bit (0) is converted into a signal point arrangement xe2x80x9c0xe2x80x9d and bit (1) is converted into a signal point arrangement xe2x80x9c4xe2x80x9d. Relations between signal point arrangements and arrangement numbers of various modulation systems are made same on the basis of 8BPSK.
I-axis and Q-axis of each of QPSK and BPSK of the hierarchical transmission system coincide with I-axis and Q-axis of 8PSK.
In case of a receiver for receiving a digital wave to be modulated (wave to be PSK-modulated) according to the hierarchical transmission system, as shown in FIG. 10, an intermediate-frequency signal IF of a signal received by a not-illustrated receiving circuit is demodulated by a demodulating circuit 1 and thus, I and Q base-band signals (hereafter also referred to as I and Q symbol-stream data) showing instantaneous values of I-axis and Q-axis orthogonal to each other for each symbol are obtained. When a frame-synchronizing signal is repeatedly captured every certain frame cycle from the demodulated I and Q base-band signals by a frame-sync detecting/regenerating circuit 2, it is judged that frame sync is established and thus, a frame-synchronizing pulse FSYNC is output or a regenerated frame-synchronizing signal is output.
Furthermore, after establishing the frame sync, the present rotation angle of the received signal can be obtained from the signal points arrangement of the frame-synchronizing part in the I, Q base-band signals captured by a frame sync detecting/regenerating circuit 2. And, any desired absolute phasing corresponding to the phase angle of a transmission signal can be established by reversely phase-rotating the I, Q base-band signals on the basis of the obtained rotation angle of the received signal.
Moreover, after frame sync is established, transmission-multiple-configuration identifying information (refer to TMCC in FIG. 7) is separated and it is identified in which modulation-system portion I and Q base-band signals are included. In accordance with the identification result, a main signal according to 8PSK modulation and a main signal according to QPSK modulation are separated from absolute-phase-generated I and Q base-band signals.
The demodulating circuit 1 orthogonally detects an intermediate-frequency signal IF by using a regenerated carrier wave and transmits I and Q base-band signals (also referred to as I and Q symbol-stream data) I(8) and Q(8) (numeral in parentheses shows the number of quantization bits and hereafter also referred to as I and Q by omitting the number of quantization bits) of eight quantization bits (two""s complement system) showing instantaneous values of I-axis and Q-axis for each symbol. The demodulating circuit 1 according to the hierarchical transmission system establishes frame sync and performs 8PSK demodulation before a modulation system is identified. After frame sync is established and a modulation system is identified, the circuit 1 performs demodulation suitable for each modulation system in accordance with the modulation system of a received signal.
In the case of the demodulating circuit 1, reception-side I- and Q-axes rotate by (xcfx80/4)xc3x97n (n is one of integers 0 to 7) against transmission-side I- and Q-axes depending on a phase state of a regenerated carrier wave for a received carrier wave and a phase of a received-signal point on I-Q phase plane according to I and Q base-band signals I(8) and Q(8) at the reception side rotates when receiving digital signals related to signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d on I-Q phase plane at the transmission side. For example, bits (0) and (1) mapped to signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d at the transmission side through BPSK mapping appear on signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d same as the transmission side when a received-signal-phase rotation angle xcex8 at the reception side is equal to 0.
However, transmission-side bits (0) and (1) appear on signal point arrangements xe2x80x9c1xe2x80x9d and xe2x80x9c5xe2x80x9d when a phase rotates by xcex8=xcfx80/4 at the reception side, appear on signal point arrangements xe2x80x9c2xe2x80x9d and xe2x80x9c6xe2x80x9d when a phase rotates by xcex8=2xcfx80/4 at the reception side, appear on signal point arrangements xe2x80x9c3xe2x80x9d and xe2x80x9c7xe2x80x9d when a phase rotates by xcex8=3xcfx80/4 at the reception side, appear on signal point arrangements xe2x80x9c4xe2x80x9d and xe2x80x9c0xe2x80x9d when a phase rotates by xcex8=4xcfx80/4 at the reception side, appear on signal point arrangements xe2x80x9c5xe2x80x9d and xe2x80x9c1xe2x80x9d when a phase rotates by xcex8=5xcfx80/4 at the reception side, appear on signal point arrangements xe2x80x9c6xe2x80x9d and xe2x80x9c2xe2x80x9d when a phase rotates by xcex8=6xcfx80/4 at the reception side, and appear on signal point arrangements xe2x80x9c7xe2x80x9d and xe2x80x9c3xe2x80x9d when a phase rotates by xcex8=7xcfx80/4 at the reception side. The frame-sync detecting/regenerating circuit 2 must correctly capture a frame-synchronizing signal even if a regenerated carrier wave of the demodulating circuit 1 has any phase state.
As shown in FIG. 10, the frame-sync detecting/regenerating circuit 2 is constituted of a BPSK demapper section 3, sync detecting circuits 40 to 47, an OR gate circuit 53, a frame-synchronizing circuit 5, and a frame-synchronizing-signal generator 6.
I and Q base-band signals I(8) and Q(8) output from the demodulating circuit 1 are input to the BPSK demapper section 3 of the frame-sync detecting/regenerating circuit 2 in order to capture a frame-synchronizing signal and bit streams B0 to B7 BPSK-demapped are output for each of eight received-signal-phase-rotation angles xcex8. The BPSK demapper section 3 is constituted of, for example, a ROM.
In the hierarchical transmission system, a frame-synchronizing signal is transmitted together with a superframe-identifying signal by being BPSK-modulated so as to minimize a required C/N. In the case of a bit stream of a frame-synchronizing signal constituted of 20 bits, W1 is equal to (S0S1 . . . S18S19)=(11101100110100101000) which are transmitted from S0 in order. The bit stream is converted to a signal point arrangement xe2x80x9c0xe2x80x9d or xe2x80x9c4xe2x80x9d through the BPSK mapping shown in FIG. 9C at the transmission side and a converted symbol stream is transmitted.
When a received-signal-phase rotation angle xcex8 is equal to 0, bit (0) of a frame-synchronizing signal appears on a signal point arrangement xe2x80x9c0xe2x80x9d and bit (1) of the signal appears on a signal point arrangement xe2x80x9c4xe2x80x9d at the reception side. To capture 20 bits, that is, a frame-synchronizing signal of 20 symbols BPSK-modulated and transmitted, it is necessary to convert received symbols into bit data through the BPSK demapping shown in FIG. 12A inversely to mapping converted at the transmission side. In FIG. 12A, (0) is judged when a received-signal point shown by I and Q base-band signals I and Q is kept in the right side of Q-axis (positive side of I-axis; refer to the hatched portion) on reception-side I-Q phase plane and (1) is judged when the received-signal point is kept in the left side of Q-axis (negative side of I-axis; refer to the unhatched portion). That is, in FIG. 12A, an output is judged as (0) or (1) depending on either of two judgement areas divided by a BPSK criterion border line (coinciding with Q-axis) shown by a bold line and thereby, it is judged that BPSK demapping is performed.
I and Q base-band signals I(8) and Q(8) are input to a BPSK demapper 30 of the BPSK demapper section 3 shown in FIG. 11 and the bit stream B0 BPSK-demapped in FIG. 12A is output from the BPSK demapper 30. In this specification, a demapper denotes a circuit for performing demapping. The bit stream B0 is input to the sync detecting circuit 40 and a bit stream of a frame-synchronizing signal is captured from the bit stream B0 in the sync detecting circuit 40.
Then, the sync detecting circuit 40 is described below by referring to FIG. 14. The sync detecting circuit 40 has 20 D-flip-flops (hereafter referred to as D-F/Fs) D19 to D0 connected in series and a 20-stage shift register is constituted of these D-F/Fs D19 to D0. The bit stream B0 is input to the D-F/F D19 and successively shifted up until the D-F/F D0. At the same time, logical inversion is applied to predetermined bits of the D-F/Fs D19 to D0 and then, outputs of the D-F/Fs D19 to D0 are input to an AND gate 51. An output SYNA0 of the AND gate 51 becomes a high potential when output states (D0D1 . . . D18D19) of the D-F/Fs D19 to D0 become (11101100110100101000). That is, when W1 is captured, SYNA0 becomes a high potential.
The output SYNA0 of the sync detecting circuit 40 is input to the frame-synchronizing circuit 5 through the OR gate circuit 53. In the frame-synchronizing circuit 5, it is judged that frame sync is established when it is confirmed that a frame-synchronizing-signal capturing signal SYNA output by the OR gate circuit 53 repeatedly becomes a high potential every certain frame cycle and a frame-synchronizing pulse FSYNC is output every frame cycle.
A received-signal-phase rotation angle xcex8 may have an angle other than 0. In this case, it is impossible to capture a frame-synchronizing signal by a combination of the BPSK demapper 30 and the sync detecting circuit 40. As shown in FIG. 11, the BPSK demapper section 3 is provided with BPSK demappers 31 to 37 corresponding to received-signal-phase rotation angles xcex8=xcfx80/4, 2xcfx80/4, 3xcfx80/4, 4xcfx80/4, 5xcfx80/4, 6xcfx80/4, and 7xcfx80/4.
FIG. 12B shows BPSK demapping when a symbol stream of a demodulated frame-synchronizing signal is phase-rotated by xcex8=xcfx80/4 and bit (0) appears on a signal point arrangement xe2x80x9c1xe2x80x9d and bit (1) appears on a signal point arrangement xe2x80x9c5xe2x80x9d. In FIG. 12B, a BPSK criterion border line shown by a bold line rotates by xcfx80/4 counterclockwise from the basic BPSK criterion border line of BPSK demapping shown by a bold line in FIG. 12A in the case of reception at the same phase as that of the transmission side. The BPSK demapper 31 performs BPSK demapping in accordance with FIG. 12B. In FIG. 12B, (0) is judged when a received-signal point shown by I and Q base-band signals I and Q is kept in the top right area of the BPSK criterion border line and (1) is judged when the received-signal point is kept in the left bottom area of the border line. A bit stream BPSK-demapped by the BPSK demapper 31 serves as an output B1 of the BPSK demapper section 3 in FIG. 10.
Similarly, the BPSK demappers 32 to 37 perform BPSK demapping at BPSK criterion border lines rotated by 2xcfx80/4, 3xcfx80/4, . . . , and 7xcfx80/4 counterclockwise from the basic BPSK criterion border line shown by a bold line of the BPSK demapping in FIG. 12A (refer to FIGS. 12C and 12D and FIGS. 13A to 13D) to stably capture frame-synchronizing signals phase-rotated by xcex8=2xcfx80/4, 3xcfx80/4, . . . , and 7xcfx80/4 against the transmission side. Bit streams BPSK-demapped by the BPSK demappers 32 to 37 serve as outputs B2 to B7 of the BPSK demapper section 3 in FIG. 10.
Configurations of the sync detecting circuits 41 to 47 are the same as the configuration of the sync detecting circuit 40. By using these sync detecting circuits 40 to 47, a frame-synchronizing signal is captured in accordance with a combination of any BPSK demapper and any sync detecting circuit independently of phase rotation of a base-band signal against the transmission side according to a phase state of a regenerated carrier wave in the demodulating circuit 1 and a high-potential signal SYNAn (n is one of integers 0 to 7) is transmitted from a sync detecting circuit of a system capturing a frame-synchronizing signal.
Signals SYNAn output from the sync detecting circuits 40 to 47 are input to the OR gate circuit 53 in which the logical sum is computed. When any signal SYNAn becomes a high potential, a high-potential frame-synchronizing-signal capturing signal SYNA showing that a frame-synchronizing signal is captured is output from the OR gate circuit 53. The frame-synchronizing circuit 5 judges that frame sync is established when it is confirmed that a high potential of SYNA is repeatedly input every certain frame interval and outputs a frame-synchronizing pulse FSYNC every frame cycle. Whenever receiving the frame-synchronizing pulse FSYNC from the frame-synchronizing circuit 5, the frame-synchronizing-signal generator 6 generates a bit stream (referred to as a regenerated frame-synchronizing signal) same as a bit pattern W1 of a frame-synchronizing signal captured by the BPSK demapper section 3 and the sync detecting circuits 40 to 47.
The process is described above in which a frame-synchronizing signal is captured from I and Q base-band signals I(8) and Q(8) output from the demodulating circuit 1 by the frame-sync detecting/regenerating circuit 2 shown in FIG. 10 and a frame-synchronizing pulse FSYNC is output after a certain time and a regenerated frame-synchronizing signal is output.
When frame sync is established, processings such as identification of a transmission multiple configuration, detection of a received-signal-phase rotation angle, and absolute phase generation for making a received-signal phase coincide with that of the transmission side are performed. For example, an operation for identifying each transmission configuration by a not-illustrated transmission-configuration identifying circuit is performed as described below. When a frame-synchronizing pulse FSYNC is output, the transmission-configuration identifying circuit captures a bit stream Bn of a system repeatedly becoming a high potential among SYNA0 to SYNA7, extracts the TMCC pattern in FIG. 9 by using a predetermined timing signal generated from the frame-synchronizing pulse FSYNC, decodes the TMCC pattern, and outputs a modulation-system identifying signal showing on which modulation system the present I and Q base-band signals I and Q depend to the demodulating circuit 1 and the like. The demodulating circuit 1 performs demodulation suitable for a modulation system of a received signal in accordance with an input modulation-system identifying signal.
However, under the worst receiving environment in which a received C/N becomes 0 dB, a transmission error rate of the BPSK modulation system becomes approx. 10xe2x88x921. Therefore, an error occurs in approx. 2 bits of a frame-synchronizing signal comprising 20 symbols. In this case, a problem occurs in the above-described conventional frame-sync detecting/regenerating circuit 2 that none of the sync detecting circuits 40 to 47 can capture a frame-synchronizing signal, thus frame sync cannot be established, and no digital signal can be received. To solve the problem, if each of the sync detecting circuits 40 to 47 outputs a frame-synchronizing signal by allowing an error of approx. several bits, a true frame-synchronizing signal cannot be captured because many patterns similar to a symbol pattern of the frame-synchronizing signal appear in I and Q symbol streams.
It is an object of the present invention to provide a frame-synchronizing-signal capturing circuit of a receiver capable of stably capturing frame-synchronizing signals even under the worst receiving environment.
The frame-synchronizing-signal capturing circuit of a receiver according to claim 1 of the present invention for capturing a frame-synchronizing signal from I and Q symbol-stream data obtained by receiving and demodulating a signal to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and a BPSK-modulated digital signal are time-multiplexed, comprises BPSK demapping means for independently BPSK-demapping I and Q symbol-stream data in accordance with four criterion border lines obtained by rotating a criterion border line for performing BPSK-demapping to bits (0) and (1) (or (1) and (0)) depending on the fact that a received-signal point according to I and Q symbol-stream data is present at right side or left side of Q-axis on I-Q phase plane by (xcfx80/4)xc3x97m (m denotes four integers selected out of integers 0 to 7 so that the four integers are not duplicated and a selected angle does not coincide with others even if it is rotated by xcfx80) and outputting bit streams of four systems; first comparing means provided for each system of outputs of the BPSK demapping means to compare a data pattern held by a shift register with a frame-synchronizing-signal pattern or an inverted-frame-synchronizing-signal pattern while inputting a bit stream to the shift register and perform correlation-detection output when there are matched numbers in bit unit equal to or more than a predetermined first specified value P and there are only matched numbers equal to or less than a predetermined second specified value R; second comparing means provided for each system output from the BPSK demapping means to compare a data pattern held by a shift register with a superframe-identifying-signal pattern or an inverted-superframe-identifying-signal pattern while inputting a bit stream to the shift register and perform correlation-detection output when there are matched numbers in bit unit equal to or more than a predetermined third specified value Pxe2x80x2 and there are only matched numbers in bit unit equal to or less than a predetermined fourth specified value Rxe2x80x2; and frame-synchronizing-signal capturing-signal generating means for outputting a frame-synchronizing-signal capturing signal when a correlation-detection output supplied from one of the first comparing means and a correlation-detection output supplied from one of the second comparing means are generated in accordance with a predetermined temporal relation.
The BPSK demapping means independently BPSK-demaps I and Q symbol-stream data in accordance with four criterion border lines obtained by rotating a basic criterion border line for performing BPSK-demapping to bits (0) and (1) (or (1) and (0)) depending on the fact that a received-signal point according to I and Q symbol-stream data is present at right side (positive side of I-axis) or left side (negative side of I-axis) of Q-axis on I-Q phase plane by (xcfx80/4)xc3x97m (m denotes four integers selected out of integers 0 to 7 so that the four integers are not duplicated and a selected angle does not coincide with others even if it is rotated by xcfx80) and outputs bit streams of four systems. When assuming that rotation angles of four criterion border lines against the basic criterion border line are equal to "THgr"1 to "THgr"4, symbol streams received at received-signal-phase rotation angles xcex8="THgr"1 and "THgr"1+xcfx80 are changed to bit streams through the demapping using a criterion border line of "THgr"1 (however, in the case of "THgr"1+xcfx80, a bit stream is obtained in which bits (0) and (1) are inverted). A symbol stream is changed to a bit stream in the case when a received-signal-phase rotation angle xcex8 is equal to 0, xcfx80/4, 2xcfx80/4, 3xcfx80/4, 4xcfx80/4, 5xcfx80/4, 6xcfx80/4, or 7xcfx80/4 in combination with the demapping using criterion border lines of "THgr"2 to "THgr"4.
The first comparing means for inputting a bit stream demapped at a criterion border line of "THgr"i (i is one of integers 1 to 4) by assuming a bit length of a frame-synchronizing signal as FL performs correction detection output when a frame-synchronizing-signal pattern is an object to be compared, a received-signal-phase rotation angle xcex8 is equal to "THgr"i, and a pattern having only a difference within (FL-P) bits from a frame-synchronizing signal appears in the bit stream and performs correlation-detection output by assuming that a pattern having only a difference within R bits from the frame-synchronizing signal unless inverted appears when a pattern matched with the frame-synchronizing signal only within R bits appears in a bit stream inverted against the transmission side and a received-signal-phase rotation angle xcex8 is equal to "THgr"i+xcfx80 (moreover, when an inverted frame-synchronizing-signal pattern is an object to be compared, a received-signal-phase rotation angle xcex8 is equal to "THgr"i, and a pattern matched with an inverted frame-synchronizing signal within only R bits appears in a bit stream, the first comparing means performs correlation-detection output by assuming that a pattern having only a difference within R bits from a frame-synchronizing signal appears and when a received-signal-phase rotation angle xcex8 is equal to "THgr"i and a pattern having only a difference within only (FL-P) bits from an inverted frame-synchronizing signal appears in a bit stream inverted against the transmission side, the first comparing means performs correlation-detection output by assuming that a pattern having only a difference within (FL-P) bits from the frame-synchronizing signal unless inverted appears).
Moreover, the second comparing means for inputting a bit stream demapped at a criterion border line of "THgr"i (i is one of integers 1 to 4) by assuming a bit length of a superframe-identifying signal as SFL performs correction detection output when a superframe-identifying-signal pattern is an object to be compared, a received-signal-phase rotation angle xcex8 is equal to "THgr"i, and a pattern having only a difference within (SFL-Pxe2x80x2) bits from a superframe-identifying signal appears in the bit stream and performs correlation-detection output by assuming that a pattern having only a difference within Rxe2x80x2 bits from the superframe-identifying signal unless inverted appears when a pattern matched with the frame-synchronizing signal only within Rxe2x80x2 bits appears in a bit stream inverted against the transmission side and a received-signal-phase rotation angle xcex8 is equal to "THgr"i+xcfx80 (moreover, when an inverted superframe-identifying-signal pattern is an object to be compared, a received-signal-phase rotation angle xcex8 is equal to "THgr"i, and a pattern matched with an inverted superframe-identifying signal within only Rxe2x80x2 bits appears in a bit stream, the second comparing means performs correlation-detection output by assuming that a pattern having only a difference within Rxe2x80x2 bits from a superframe-identifying signal unless inverted appears and moreover, when a received-signal-phase rotation angle xcex8 is equal to "THgr"i+xcfx80 and a pattern having only a difference within only (SFL-Pxe2x80x2) bits from an inverted superframe-identifying signal appears in a bit stream inverted against the transmission side, the second comparing means performs correlation-detection output by assuming that a pattern having only a difference within (SFL-Pxe2x80x2) bits from the superframe-identifying signal unless inverted appears).
The frame-synchronizing-signal capturing-signal generating means outputs a frame-synchronizing-signal capturing signal when correlation-detection output from one of the first comparing means and correlation-detection output from one of the second comparing means are generated in accordance with a predetermined time relation.
In the case of the hierarchical transmission system, a frame-synchronizing signal and a superframe-identifying signal are arranged in one frame in accordance with a predetermined positional relation. When a pattern having a difference of only one bit to several bits from a pattern of a frame-synchronizing signal and a pattern having a difference of only one bit to several bits from the pattern of the frame-synchronizing signal appear in demodulated I and Q symbol-stream data in accordance with a predetermined time relation specified by a frame format, the pattern having a difference of only one bit to several bits from the pattern of the frame-synchronizing signal has a very high possibility that the pattern is a frame-synchronizing signal. Therefore, when correlation-detection output from one of the first comparing means and correlation-detection output from one of the second comparing means are generated in accordance with a predetermined time relation, it is possible to stably capture frame-synchronizing signals by outputting a frame-synchronizing-signal capturing signal and therefore, reception is not made impossible.
The frame-synchronizing-signal capturing circuit of a receiver according to claim 2 of the present invention comprises BPSK demapping means for independently BPSK-demapping I and Q symbol-stream data in accordance with four criterion border lines obtained by rotating a criterion border line for performing BPSK-demapping to bits (0) and (1) (or (1) and (0)) depending on the fact that a received-signal point according to I and Q symbol-stream data is present at right side or left side of Q-axis on I-Q phase plane by (xcfx80/4)xc3x97m (m denotes four integers selected out of integers 0 to 7 so that the four integers are not duplicated and a selected angle does not coincide with others even if it is rotated by xcfx80) and outputting bit streams of four systems; comparing means provided for each system of outputs of the BPSK demapping means to compare a data pattern held by a shift register with a frame-synchronizing-signal pattern or an inverted-frame-synchronizing-signal pattern while inputting a bit stream to the shift register and perform correlation-detection output when there are matched numbers in bit unit equal to or more than a predetermined first specified value P and there are only matched numbers equal to or less than a predetermined second specified value R; and frame-synchronizing-signal-capturing-signal generating means for outputting a frame-synchronizing-signal capturing signal when correlation-detection output is generated from one of comparing means and thereafter, correlation-detection output is generated again from one of the comparing means again at a timing when elapsing by a predetermined time.
In the case of the hierarchical transmission system, a frame-synchronizing signal is set to a predetermined position in one frame. When a pattern having a difference of only one bit to several bits from a pattern of the frame-synchronizing signal appears in demodulated I and Q symbol-stream data every frame cycle, the pattern having a difference of only one bit to several bits from the pattern of the frame-synchronizing signal has a very high possibility that it is a frame-synchronizing signal. Therefore, when correlation-detection output is generated from one of comparing means and thereafter, correction detection output is generated again from one of the comparing means at a timing when elapsing by a predetermined time such as one frame cycle or two frame cycles, it is possible to stably capture frame-synchronizing signals by outputting a frame-synchronizing-signal capturing signal and therefore, reception is not made impossible.
The frame-synchronizing-signal capturing circuit of a receiver according to claim 3 of the present invention comprises BPSK demapping means for independently BPSK-demapping I and Q symbol-stream data to output bit streams of four systems in accordance with four criterion border lines obtained by rotating a criterion border line for performing BPSK-demapping to bits (0) and (1) (or (1) and (0)) depending on the fact that a received-signal point according to I and Q symbol-stream data is present at right side or left side of Q-axis on I-Q phase plane by (xcfx80/4)xc3x97m (m denotes four integers selected out of integers 0 to 7 so that the four integers are not duplicated and a selected angle does not coincide with others even if it is rotated by xcfx80); comparing means provided for each system of outputs of the BPSK demapping means to compare a data pattern held by a shift register with a superframe-identifying-signal pattern or an inverted-superframe-identifying-signal pattern while inputting a bit stream to the shift register and perform correlation-detection output when there are matched numbers in bit unit equal to or more than a predetermined specified value Pxe2x80x2 and there are only matched numbers equal to or less than a predetermined specified value Rxe2x80x2; and frame-synchronizing-signal-capturing-signal generating means for outputting a temporary frame-synchronizing-signal capturing signal when a correlation-detection output is generated from one of the comparing means and thereafter, a correlation-detection output is generated again from one of the comparing means at a timing when elapsing by a predetermined time.
In the case of the hierarchical transmission system, a frame-synchronizing signal and a superframe-identifying signal are set to predetermined positions in one frame. When a pattern having a difference of only one bit to several bits from a pattern of the superframe-identifying signal appears in demodulated I and Q symbol-stream data every frame cycle, the pattern having a difference of only one bit to several bits from the pattern of the superframe-identifying signal has a very high possibility that it is a superframe-synchronizing signal and a posisibility that a frame-synchronizing signal appears in accordance with a certain time relation is very high. Therefore, when correlation-detection output is generated from one of the comparing means and thereafter, correlation-detection output is generated again from one of the comparing means at a timing when elapsing by a predetermined time such as one frame cycle, two frame cycles, or one superframe cycle, it is possible to stably capture frame-synchronizing signals by outputting a temporary frame-synchronizing-signal capturing signal and therefore, reception is not disabled.